PLL devices are core elements for frequency synthesizers implemented in electronic circuits or radio-transmission units. There is a need for reducing the lock time and improving the operation stability of PLL devices.
A PLL device with bang-bang non-linear phase detector can generally operate in two successive operation modes from an initial start. The first operation mode may be a relaxation-oscillation mode where a phase error between a reference signal and a frequency-converted signal oscillates back and forth. This relaxation-oscillation mode splits itself into a lock acquisition phase where a lock state is not yet reached, and then a lock phase where the lock state is continually maintained so that the frequency-converted signal remains close in frequency to the reference signal. Operation stability is necessary for avoiding loss of the lock state. Otherwise, lock acquisition is started over, wasting time until the clock signal which is produced by the PLL device can be used again. For obtaining operation stability in combination with low noise in the phase of the PLL-produced clock signal, the open-loop gain of the PLL device has to be reduced. However, continuing to decrease the phase oscillation magnitude leads to capturing noise within the loop-control of the frequency of the PLL-produced clock signal. This is a random noise operation mode which occurs once the lock state is continually obtained while reducing the open-loop gain of the PLL device by a sufficient reduction extent. In this mode, the analog jitter sources generate significant dithering of the non-linearity of the phase detector, the phase detector behaving as a linear device for signals of frequency components negligible with respect to the sampling frequency (in practice, typically ten times smaller). The PLL phase error is such a signal.
There is a need for PLL devices which are capable of operating in the random noise operation mode as quickly as possible after the lock acquisition phase has started.
Additionally, each of the lock acquisition phase, lock phase, and random noise operation mode requires gain values for a proportional-integral loop filter implemented in the PLL device, which are different for obtaining minimum lock acquisition time and improved stability.
U.S. Pat. No. 8,203,369 describes a PLL device which is capable of linearizing the PLL response for a large phase error, so that the lock acquisition phase is performed more rapidly. This PLL device implements measuring of a duration between two successive sign reversals of the phase error, and combining the measured duration with the error signal itself before it is fed into the loop filter. However, such a PLL device does not detect that the lock state is actually obtained, and it cannot reach the random noise operation mode.
One object of the present invention is to provide a PLL device which is capable of reaching the random noise operation mode in a reliable and rapid manner. For example, the PLL device should perform the lock acquisition phase quickly and then maintain the lock state as long as possible including during the random noise operation.
Another object of the invention is for the PLL device to be capable of recovering the random noise operation mode automatically and as quickly as possible when the lock state has been lost.